Computer organization and architecture miscellaneous

Computer organization and architecture miscellaneous

Easy Questions

Computer Organization and Architecture

Computer organization and architecture miscellaneous
  1. Register renaming is done in pipelined processors








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    Pipelining of the register renaming logic can help avoid restricting the processor clock frequency.

    Correct Option: C

    Pipelining of the register renaming logic can help avoid restricting the processor clock frequency.

  1. Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1 : Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
    P2 : Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
    P3 : Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
    P4 : Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
    Which processor has the highest peak clock frequency ?








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    Frequency ∝
    1
    clock period

    Clock period = maximum stage delay + overhead
    P1 : CP = Max (1, 2, 2, 1) = 2 ns
    P2 : CP = Max (1, 1.5, 1.5, 1.5) = 1.5 ns
    P3 : CP = Max (0.5, 1, 1, 0.6, 1) = 1 ns
    P4 : CP = Max (0.5, 0.5, 1, 1, 1, 1) = 1.1 ns
    ∵ CP of P3 is less, it has highest frequency
    Frequency 1 P3 =
    1
    		 = 1 GHz
    1 ns

    Correct Option: C

    Frequency ∝
    1
    clock period

    Clock period = maximum stage delay + overhead
    P1 : CP = Max (1, 2, 2, 1) = 2 ns
    P2 : CP = Max (1, 1.5, 1.5, 1.5) = 1.5 ns
    P3 : CP = Max (0.5, 1, 1, 0.6, 1) = 1 ns
    P4 : CP = Max (0.5, 0.5, 1, 1, 1, 1) = 1.1 ns
    ∵ CP of P3 is less, it has highest frequency
    Frequency 1 P3 =
    1
    		 = 1 GHz
    1 ns

  1. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3,..., I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is








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    Instruction pipeline with five stages without any branch predicition : Delays for FI, DI, FO.EI and WO are 5,7,10,8,6 ns respectively. The maximum time taken by any stage is 10 ns and additional 1ns is required for delay of buffer.
    ∴ The total time for an instruction to pass from one stage to another in 11 ns.
    The instructions are executed in the following order l1, l2, l3 , l4 , l9 , l10, l11, l12
    Execution with Time
    Now when l4 is in its execution stage we detect the branch and when l4 is in WO stage we fetch I9 so time for execution of instructions from l9 to l12 is = 11* 5 +(4 – 1) * 11= 88 ns.
    But we save 11 ns when fetching l9 i.e., l9 requires only 44 ns additional instead of 55 ns because time for fetching l9 can be overlap with WO of l4.
    ∴ Total Time is = 88 + 88 – 11 = 165 ns

    Correct Option: B

    Instruction pipeline with five stages without any branch predicition : Delays for FI, DI, FO.EI and WO are 5,7,10,8,6 ns respectively. The maximum time taken by any stage is 10 ns and additional 1ns is required for delay of buffer.
    ∴ The total time for an instruction to pass from one stage to another in 11 ns.
    The instructions are executed in the following order l1, l2, l3 , l4 , l9 , l10, l11, l12
    Execution with Time
    Now when l4 is in its execution stage we detect the branch and when l4 is in WO stage we fetch I9 so time for execution of instructions from l9 to l12 is = 11* 5 +(4 – 1) * 11= 88 ns.
    But we save 11 ns when fetching l9 i.e., l9 requires only 44 ns additional instead of 55 ns because time for fetching l9 can be overlap with WO of l4.
    ∴ Total Time is = 88 + 88 – 11 = 165 ns

  1. Consider the following sequence of micro-operations.
    MBR ← PC
    MAR ← X
    PC ← Y
    Memory ← MBR
    Which one of the following is a possible operation performed by this sequence ?








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    The following sequence of micro-operations
    MBR       ← PC
    MAR     ← X
    PC ←     Y
    Memory     ← MBR.
    Analysis
    1. First micro operation stores the value of PC into Memory Base Register (MBR).
    2. Second micro operation stores the value of X into Memory Address Resister (MAR).
    3. Third micro operation stores value of Y into PC.
    4. Fourth micro operation stores value of MBR to memory.
    So before execution of these instructions PC holds the value of next instruction to be executed. We first stores the value of PC to MBR and then through MBR to memory i.e., We are saving the value of PC in memory and then load PC with a new value. This can be done only in two types. Operations Conditional branch and interrupt service.
    As we are not checking here for any conditions. So, it is an Initiation of interrupt service.

    Correct Option: D

    The following sequence of micro-operations
    MBR       ← PC
    MAR     ← X
    PC ←     Y
    Memory     ← MBR.
    Analysis
    1. First micro operation stores the value of PC into Memory Base Register (MBR).
    2. Second micro operation stores the value of X into Memory Address Resister (MAR).
    3. Third micro operation stores value of Y into PC.
    4. Fourth micro operation stores value of MBR to memory.
    So before execution of these instructions PC holds the value of next instruction to be executed. We first stores the value of PC to MBR and then through MBR to memory i.e., We are saving the value of PC in memory and then load PC with a new value. This can be done only in two types. Operations Conditional branch and interrupt service.
    As we are not checking here for any conditions. So, it is an Initiation of interrupt service.

  1. A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of the instructions ?
    Instruction Meaning of instruction
    I0 : MUL R2, R0 , R1R2 →     R0 * R1
    I1 : DIV R5, R3, R4 R5 →     R3 / R4
    I2 : ADD R2 , R5, R2 R2 →     R5 + R2
    I3 : SUB R5, R2, R6R5 →     R2 – R6









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    As per the given, the instructions are arranged accordingly to their meanings. We get the following :

    Here, we can see that the last operation (Write Operand) comes at the 15th clock cycle so it takes 15 clock cycles to execute given sequence of instructions.

    Correct Option: B

    As per the given, the instructions are arranged accordingly to their meanings. We get the following :

    Here, we can see that the last operation (Write Operand) comes at the 15th clock cycle so it takes 15 clock cycles to execute given sequence of instructions.