Computer organization and architecture miscellaneous

Computer organization and architecture miscellaneous

Easy Questions

Computer Organization and Architecture

Computer organization and architecture miscellaneous
  1. Consider the following reservation table for a pipeline having three stages S1, S2, and S3.

    The Minimum Average Latency (MAL) is _____.








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    NA

    Correct Option: D

    NA

  1. Consider a 6-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this 6-stage pipeline, the speedup achieved with respect to non-pipelined execution if 25% of the instructions incur 2 pipeline stall cycles is ______________________.








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    4 to 4

    Correct Option: B

    4 to 4

  1. Consider a pipelined processor with the following four stages
    IF : Instruction Fetch
    ID : Instruction Decode and Operand Fetch
    EX : Execute
    WB : Write Black
    The IF, ID and WB stages take 1 clock cycle each to complete the operation.
    ⚈   The number of clock cycle for the EX stage depends on the instruction. the ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions:









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    As given the pipelined processor has four stages i.e., IF, ID, EX, WB, And we know that number of clock cycles required to ADD and SUB instructions is 1 and by MUL instructions are 3.
    In the pipelined processor while one instruction is fetched, the other is either being decoded or executed or some action is being performed. Thus, the number of cycles required by the given set of instructions can be obtained from the following diagram.

    Thus, total number of clock cycles required are 8.

    Correct Option: B

    As given the pipelined processor has four stages i.e., IF, ID, EX, WB, And we know that number of clock cycles required to ADD and SUB instructions is 1 and by MUL instructions are 3.
    In the pipelined processor while one instruction is fetched, the other is either being decoded or executed or some action is being performed. Thus, the number of cycles required by the given set of instructions can be obtained from the following diagram.

    Thus, total number of clock cycles required are 8.

  1. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target addresses and evaluates the condition in the third stage of the pipeline. The processor stop fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is








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    In the 3rd stage of pipeline, there will be 2 shall cycles.
    Total number of instructions = 109, 20% out of 109 are conditional branches. Therefore, cycle penalty = 0.2 * 2 * 109 = 4 * 108.
    Clock speed is 1GHz and each instruction on average takes 1 cycle. so

    Total execution time =
    109
    		 + 4*
    108
    109109

    = 1 + (0.4) = 1.4 sec

    Correct Option: C

    In the 3rd stage of pipeline, there will be 2 shall cycles.
    Total number of instructions = 109, 20% out of 109 are conditional branches. Therefore, cycle penalty = 0.2 * 2 * 109 = 4 * 108.
    Clock speed is 1GHz and each instruction on average takes 1 cycle. so

    Total execution time =
    109
    		 + 4*
    108
    109109

    = 1 + (0.4) = 1.4 sec

  1. A 5 stage pipelined CPU has the following sequence of stages
    IF : Instruction fetch from instruction memory
    RD : Instruction decode and register read
    EX: Execute: ALU operations for data and address computation
    MA : Data memory access : for write access, the register read at RD stage is used
    WB : Register write back
    Consider the following sequence of instructions :
    I1 : L R0 loc 1; R0 < = M [loc1]
    I2 : A R0 ; R0 ; R0 < = R0 + R0
    I3 : S R2; R0 ; R2 < = R2 – R0
    Let each state takes on clock cycle.
    What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?








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    Thus, total number of clock cycles required = 10

    Correct Option: A


    Thus, total number of clock cycles required = 10