Computer organization and architecture miscellaneous

Computer organization and architecture miscellaneous

Easy Questions

Computer Organization and Architecture

Computer organization and architecture miscellaneous
  1. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target addresses and evaluates the condition in the third stage of the pipeline. The processor stop fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is








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    In the 3rd stage of pipeline, there will be 2 shall cycles.
    Total number of instructions = 109, 20% out of 109 are conditional branches. Therefore, cycle penalty = 0.2 * 2 * 109 = 4 * 108.
    Clock speed is 1GHz and each instruction on average takes 1 cycle. so

    Total execution time =
    109
    		 + 4*
    108
    109109

    = 1 + (0.4) = 1.4 sec

    Correct Option: C

    In the 3rd stage of pipeline, there will be 2 shall cycles.
    Total number of instructions = 109, 20% out of 109 are conditional branches. Therefore, cycle penalty = 0.2 * 2 * 109 = 4 * 108.
    Clock speed is 1GHz and each instruction on average takes 1 cycle. so

    Total execution time =
    109
    		 + 4*
    108
    109109

    = 1 + (0.4) = 1.4 sec

  1. An instruction pipeline has five stages where each stage takes 2 nanoseconds and all instructions use all five stages. Branch instructions are not overlapped, i.e., the instruction after the branch is not fetched till the branch instruction is completed. Under ideal conditions.
    (a) Calculate the average instruction execution time assuming that 20% of all instruction executed are branch instructions. Ignore the fact that some branch instructions may be conditional.
    (b) If a branch instruction is a conditional branch instruction, the branch need not be taken. If the branch is not taken, the following instructions can be overlapped. When 80% of all branch instructions are conditional branch instructions, and 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction time.








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    (a) 3.6 nano seconds (b) 2.96 nano seconds

    Correct Option: C

    (a) 3.6 nano seconds (b) 2.96 nano seconds

  1. Consider a two-level cache hierarchy with LI and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is________.








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    As given that, an application incurs 1.4 memory accesses per instruction.
    So, the Number of memory Accesses in 1000 instructions is
    = 1.4 × 1000 = 1400.
    Number of Misses in L2 cache

    =
    Miss per instructions
    Number of Memory Accesses

    =
    7 Miss (Per 1000 instruction)
    		 = 0.005
    1400 (Memory Accesses)

    Miss rate L2 =
    Miss in L2
    Miss in L1

    ∴ (given, Miss rate of L1 cache is 0.1)
    So , L2 =
    0.005
    0.1

    Miss in L2 = 0.05

    Correct Option: A

    As given that, an application incurs 1.4 memory accesses per instruction.
    So, the Number of memory Accesses in 1000 instructions is
    = 1.4 × 1000 = 1400.
    Number of Misses in L2 cache

    =
    Miss per instructions
    Number of Memory Accesses

    =
    7 Miss (Per 1000 instruction)
    		 = 0.005
    1400 (Memory Accesses)

    Miss rate L2 =
    Miss in L2
    Miss in L1

    ∴ (given, Miss rate of L1 cache is 0.1)
    So , L2 =
    0.005
    0.1

    Miss in L2 = 0.05

  1. The following code is to run on a pipelined processor with one branch delay slot :
    l1 : ADD R2 < R7 + R8
    l2 : SUB R4 ← R5 – R6
    l3 : ADD R1 ← R2 + R3
    l4 : STORE Memory [R4] ← R1
    BRANCH to Label if R1 = 0
    Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?








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    I4, the store instruction can be moved below the conditional branch instruction. whether the branch is taken or not, STORE will be executed as the next instruction after conditional branch instruction, due to delayed branching. Here, I3 is not the answer because the branch conditional variable R1 is dependent on it. same for I1, similarly, I4 has a dependency on I2 and hence I2 must be executed before I 4

    Correct Option: D

    I4, the store instruction can be moved below the conditional branch instruction. whether the branch is taken or not, STORE will be executed as the next instruction after conditional branch instruction, due to delayed branching. Here, I3 is not the answer because the branch conditional variable R1 is dependent on it. same for I1, similarly, I4 has a dependency on I2 and hence I2 must be executed before I 4

  1. The performance of a pipelined processor suffers if








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    Pipelining is a method to execute a program breaking it in several independent sequence of stages. In that case pipeline stages can't have different delays, no dependency among consecutive instructions & sharing of hardware resources shouldn't be there. So option (d) is true.

    Correct Option: D

    Pipelining is a method to execute a program breaking it in several independent sequence of stages. In that case pipeline stages can't have different delays, no dependency among consecutive instructions & sharing of hardware resources shouldn't be there. So option (d) is true.