The following code is to run on a pipelined processor with

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The following code is to run on a pipelined processor with one branch delay slot :
l₁ : ADD R₂ < R₇ + R₈
l₂ : SUB R₄ ← R₅ – R₆
l₃ : ADD R₁ ← R₂ + R₃
l₄ : STORE Memory [R₄] ← R₁
BRANCH to Label if R₁ = 0
Which of the instructions I₁, I₂, I₃ or I₄ can legitimately occupy the delay slot without any other program modification?

1. I₁
2. I₂
3. I₃
4. I₄

Correct Option: D

I4, the store instruction can be moved below the conditional branch instruction. whether the branch is taken or not, STORE will be executed as the next instruction after conditional branch instruction, due to delayed branching. Here, I3 is not the answer because the branch conditional variable R1 is dependent on it. same for I1, similarly, I4 has a dependency on I2 and hence I2 must be executed before I 4