Computer organization and architecture miscellaneous

Computer organization and architecture miscellaneous

Easy Questions

Computer Organization and Architecture

Computer organization and architecture miscellaneous
  1. The micro-instructions stored in the control memory of a processor have a width of 26 bit. Each micro-instruction is divided into three fields; a micro-operation field of 13 bit, a next address field (X), and a MUX select field (Y), there are 8 status bits in the inputs of the MUX.

    How many bits are there in the X and Y fields, and what in the size of the control memory in number of words?








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    MUX has 8 states bits as input lines so we require 3 select inputs to select & input lines. No. of bits in control memory next address field = 26 – 13 – 3
    = 10
    10 bit addressing, we have 210 memory size. So X, Y size = 10,3,1024
    Hence (a) is correct option.

    Correct Option: A

    MUX has 8 states bits as input lines so we require 3 select inputs to select & input lines. No. of bits in control memory next address field = 26 – 13 – 3
    = 10
    10 bit addressing, we have 210 memory size. So X, Y size = 10,3,1024
    Hence (a) is correct option.

  1. Consider the following data path of a simple non-pipelined CPU. The registers A, B, A1, A2, MDR, the bus and the ALU are 8-bit wide, SP and MAR are 16 - bit registers. The MUX is of size 8 × (2: 1) and the DEMUX is of size 8 × (1: 2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally.

    The CPU instruction “ Push r”, where = A or B, has the specification
    M [SP] ← r
    SP ← SP – 1
    How many CPU clock cycles are needed to execute the “push r” instruction?








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    Push 'r'
    Consist of following operations
    M [SP] !r
    SP! SP – 1
    'r' is stored at memory at address stack pointer currently is, this take 2 clock cycles.
    SP is then decremented to point to next top of stack. So total cycles = 3
    Hence (b) is correct option.

    Correct Option: B

    Push 'r'
    Consist of following operations
    M [SP] !r
    SP! SP – 1
    'r' is stored at memory at address stack pointer currently is, this take 2 clock cycles.
    SP is then decremented to point to next top of stack. So total cycles = 3
    Hence (b) is correct option.

  1. Consider the ALU shown below :
    If the operands are in 2’s complement representation, which of the following operations can be performed by suitably setting the control lines K and C0 only (+ and – denote addition and subtraction respectively)?








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    Case I :- If k = 1, that means output of EX-OR gate is in complemented form. If add 1 (by setting CO = 1) to this complemented form then it becomes 2S complement of B. now adding A to the 2’S complement of B is nothing but subtraction.
    Case II :- If k = 0, EX-OR Simply return B. Add A to B without setting co i.e, K = 0,
    C 0 = 0, return addition of A and B ⇒ (A+ B)
    Case III :- We cannot increment A value without changing B content So A + 1 is not possible with given condition. Hence option (A) is correct.

    Correct Option: A

    Case I :- If k = 1, that means output of EX-OR gate is in complemented form. If add 1 (by setting CO = 1) to this complemented form then it becomes 2S complement of B. now adding A to the 2’S complement of B is nothing but subtraction.
    Case II :- If k = 0, EX-OR Simply return B. Add A to B without setting co i.e, K = 0,
    C 0 = 0, return addition of A and B ⇒ (A+ B)
    Case III :- We cannot increment A value without changing B content So A + 1 is not possible with given condition. Hence option (A) is correct.

Direction: Consider the following data path of a CPU :

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory bus into the MDR.

  1. The instruction “CALL Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is Rn < = PC + 1 PC < = M [PC]
    The minimum number of CPU clock cycles needed during the execution cycle of this instruction is








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    The minimum number of CPU clock cycles needed during the execution cycle = 4 As 1 cycle required to transfer already incremented value of PC and 2 cycle for getting data in MDR1 to load value of MDR in PC.

    Correct Option: B

    The minimum number of CPU clock cycles needed during the execution cycle = 4 As 1 cycle required to transfer already incremented value of PC and 2 cycle for getting data in MDR1 to load value of MDR in PC.

  1. The instruction “ADD R0, R1 ” has the register transfer interpretation R0 < = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is








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    Given that R0 ← R0 + R1 The clock cycles operate as follows :

    Cycle 1 Out : R1
    In : S
    Cycle 2 Out : R2
    In : T
    Cycle 3 Out : S, T
    Add : ALU
    In : R

    Therefore, execution cycle is completed in 3 clock cycles.

    Correct Option: B

    Given that R0 ← R0 + R1 The clock cycles operate as follows :

    Cycle 1 Out : R1
    In : S
    Cycle 2 Out : R2
    In : T
    Cycle 3 Out : S, T
    Add : ALU
    In : R

    Therefore, execution cycle is completed in 3 clock cycles.