Computer organization and architecture miscellaneous


Computer organization and architecture miscellaneous

Computer Organization and Architecture

  1. A processor can support a maximum memory of 4 GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _________bits.









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    Maximum memory = 4 GB = 232 bytes
    Size of a word = 2 bytes
    Therefore, Number of words = 232 / 2 = 231
    So, we require 31 bits for the address bus of the processor.

    Correct Option: A

    Maximum memory = 4 GB = 232 bytes
    Size of a word = 2 bytes
    Therefore, Number of words = 232 / 2 = 231
    So, we require 31 bits for the address bus of the processor.


  1. Consider the following 8085 program segment, where registers B and C contain BCD values :

    (a) For the two pairs (B = 44, C = 25) and (B = 33, C = 46) at S1,
    (i) Find the values in register A when control reaches S2.
    (ii) Find the values in registers D and E when control reaches S4.
    (b) What, in general, is the value of D and E as a function of B and C when control reaches S4.









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    (a) (i) 18 H     86H
    (ii) D = 00H     D = FFH
    E = 19H     E 13H
    (b) E = | B – C |
    D = 00H     if B > C
    and D = FFH     if B < C

    Correct Option: D

    (a) (i) 18 H     86H
    (ii) D = 00H     D = FFH
    E = 19H     E 13H
    (b) E = | B – C |
    D = 00H     if B > C
    and D = FFH     if B < C



  1. Consider the 8085 instruction IN 09H stored as follows:

    Add the following incomplete timing diagram for the instruction :

    (a) Write the contents of the boxes, A, B, C and D in hexademcimal in your answer sheet do not draw any pictures.
    (b) Write the state of both ALE and RD pins at times T1, T2, T3 and T4. (c) How do you generate the signal that tells the peripheral to put the data on the bus? Answer by completing the following statement in your answer book : By combining signals ..............









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    (a) A : D A H     B : 0 9 H
    C : 0 9 H     D : 5 1 H
    (b) ALE : T1 = 1
    T2 = T3 = T4 = 0
    RD : T1 = 1
    T2 = T3 = 0. T4 = 1
    (c) The IO/ M signal and RD signal

    Correct Option: D

    (a) A : D A H     B : 0 9 H
    C : 0 9 H     D : 5 1 H
    (b) ALE : T1 = 1
    T2 = T3 = T4 = 0
    RD : T1 = 1
    T2 = T3 = 0. T4 = 1
    (c) The IO/ M signal and RD signal


  1. Which is the most appropriate match for the items in the first column with the items in the second column?










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    Indexed addressing is used for array implementation where each element has indexes. Base register is used to re-locatable code, where starts from base address & then all local addresses as added to base address.
    Indirect addressing is done when array is passed as parameter only name is passed. Hence (a) is correct option.

    Correct Option: A

    Indexed addressing is used for array implementation where each element has indexes. Base register is used to re-locatable code, where starts from base address & then all local addresses as added to base address.
    Indirect addressing is done when array is passed as parameter only name is passed. Hence (a) is correct option.



  1. Horizontal micro – programming









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    In horizontal microprogramming the instruction size is less as compared to vertical microprogramming. So, there is no need for decoding. But one bit is used for all control signals to execute the microinstruction. If the bit is set to '1' the control signal field is activated. If the bit is set to 'O', the control signal field is deactivated.

    Correct Option: D

    In horizontal microprogramming the instruction size is less as compared to vertical microprogramming. So, there is no need for decoding. But one bit is used for all control signals to execute the microinstruction. If the bit is set to '1' the control signal field is activated. If the bit is set to 'O', the control signal field is deactivated.