Computer organization and architecture miscellaneous

Computer organization and architecture miscellaneous

Easy Questions

Computer Organization and Architecture

Computer organization and architecture miscellaneous
  1. A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ______ .








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    (i) Given is 32-bit architecture machine with 1 word long instruction; so, the instruction size is 32 bit.

    (ii) As the machine need to support 45 instructions, the number of bits required in the “opcode field” is 6 bits, because,
    5-bits: 25 = 32 (Not sufficient)
    6-bits: 26 = 64 (Sufficient)
    (iii) As the machine has 64 registers, so to uniquely identify a register out of those 64 registers, we need 6-bits. (using the similar argument as above) As each instruction has 2 register operands, so 6 + 6 = 12 bits are needed for them. So, finally instruction will took like as follows:

    (Total = 32 bits)
    (iv) As 14-bits are available for immediate operand, the max value will be 214 = 16384. However one value will be used for “Zero” also as the operand is an “unsigned integer”. So, finally, the maximum value that the immediate operand can take = 214 – 1 = 16383.

    Correct Option: C

    (i) Given is 32-bit architecture machine with 1 word long instruction; so, the instruction size is 32 bit.

    (ii) As the machine need to support 45 instructions, the number of bits required in the “opcode field” is 6 bits, because,
    5-bits: 25 = 32 (Not sufficient)
    6-bits: 26 = 64 (Sufficient)
    (iii) As the machine has 64 registers, so to uniquely identify a register out of those 64 registers, we need 6-bits. (using the similar argument as above) As each instruction has 2 register operands, so 6 + 6 = 12 bits are needed for them. So, finally instruction will took like as follows:

    (Total = 32 bits)
    (iv) As 14-bits are available for immediate operand, the max value will be 214 = 16384. However one value will be used for “Zero” also as the operand is an “unsigned integer”. So, finally, the maximum value that the immediate operand can take = 214 – 1 = 16383.

  1. An access sequence of cache block addresses is of length N and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by k. What is the miss ratio if the access sequence is passed through a cache of associativity A ≥ k exercising least-recently-used replacement policy?








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    n
    N

    Correct Option: A

    n
    N

  1. Consider a hypothetical processor with an instruction of type LW (R1), 20 (R2). which during execution reads a 32- bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instrument for the operand in memory?








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    The addressing mode will be base index addressing. Here, 20 will work as base and content of R2 will be index. R2 is base regester here and indexing is done by adding 20 to the contents of R2.

    Correct Option: D

    The addressing mode will be base index addressing. Here, 20 will work as base and content of R2 will be index. R2 is base regester here and indexing is done by adding 20 to the contents of R2.

  1. Which of the following is/are true of the auto-increment addressing mode?
    1. It is used in creating self-relocating code.
    2. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation.
    3. The amount of increment depends on the size of the data item accessed.








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    For incrementing the data, the auto-increment addressing mode is used which purely depends on the size of the data. For example:
    Regs [R1] ← Regs [R1] + Mem [Regs [R2]
    Regs [R2] ← Regs [R2] + d

    Correct Option: C

    For incrementing the data, the auto-increment addressing mode is used which purely depends on the size of the data. For example:
    Regs [R1] ← Regs [R1] + Mem [Regs [R2]
    Regs [R2] ← Regs [R2] + d

  1. Which of the following must be true for the REF (Return From Exception)
    1. It must be a TRAP instruction.
    2. It must be a privileged instruction.
    3. An exception cannot be allowed to occur during execution of an REE instruction.








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    When an RFE (Return From Exception) instruction is executed; no exception is allowed to occur during that time and also it must be a trap instruction and also a privileged one.
    Thus all the three statements are true as far as RFE is concerned.

    Correct Option: D

    When an RFE (Return From Exception) instruction is executed; no exception is allowed to occur during that time and also it must be a trap instruction and also a privileged one.
    Thus all the three statements are true as far as RFE is concerned.