Computer organization and architecture miscellaneous
- Consider a hypothetical processor with an instruction of type LW (R1), 20 (R2). which during execution reads a 32- bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instrument for the operand in memory?
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The addressing mode will be base index addressing. Here, 20 will work as base and content of R2 will be index. R2 is base regester here and indexing is done by adding 20 to the contents of R2.
Correct Option: D
The addressing mode will be base index addressing. Here, 20 will work as base and content of R2 will be index. R2 is base regester here and indexing is done by adding 20 to the contents of R2.
- An access sequence of cache block addresses is of length N and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by k. What is the miss ratio if the access sequence is passed through a cache of associativity A ≥ k exercising least-recently-used replacement policy?
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n N Correct Option: A
n N
- A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ______ .
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(i) Given is 32-bit architecture machine with 1 word long instruction; so, the instruction size is 32 bit.
(ii) As the machine need to support 45 instructions, the number of bits required in the “opcode field” is 6 bits, because,
5-bits: 25 = 32 (Not sufficient)
6-bits: 26 = 64 (Sufficient)
(iii) As the machine has 64 registers, so to uniquely identify a register out of those 64 registers, we need 6-bits. (using the similar argument as above) As each instruction has 2 register operands, so 6 + 6 = 12 bits are needed for them. So, finally instruction will took like as follows:
(Total = 32 bits)
(iv) As 14-bits are available for immediate operand, the max value will be 214 = 16384. However one value will be used for “Zero” also as the operand is an “unsigned integer”. So, finally, the maximum value that the immediate operand can take = 214 – 1 = 16383.Correct Option: C
(i) Given is 32-bit architecture machine with 1 word long instruction; so, the instruction size is 32 bit.
(ii) As the machine need to support 45 instructions, the number of bits required in the “opcode field” is 6 bits, because,
5-bits: 25 = 32 (Not sufficient)
6-bits: 26 = 64 (Sufficient)
(iii) As the machine has 64 registers, so to uniquely identify a register out of those 64 registers, we need 6-bits. (using the similar argument as above) As each instruction has 2 register operands, so 6 + 6 = 12 bits are needed for them. So, finally instruction will took like as follows:
(Total = 32 bits)
(iv) As 14-bits are available for immediate operand, the max value will be 214 = 16384. However one value will be used for “Zero” also as the operand is an “unsigned integer”. So, finally, the maximum value that the immediate operand can take = 214 – 1 = 16383.
- Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.
OP Ri, Rj, Rk
Where operation Op is performed on contents of registers Rj and Rk and the result is stored in register Ri.
I1: ADD R1, R2, R3
I2: MUL R7, R1, R3
I3: SUB R4, R1, R5
I4: ADD R3, R2, R4
I5: MUL R7, R8, R9
Consider the following three statements.
S1: There is an anti-dependence between instruction I2 and I5
S2: There is an anti-dependence between instructions I2 and I4
S3: Within an instruction pipeline an anti-dependence always creates one or more stalls Which one of above statements is/are correct?
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(I1) R1 ← R2 + R3
(I2) R7 ← R1 × R3
(I3) R4 ← R1 – R5
(I4) R3 ← R2 + R4
(I5) R7 ← R8 × R9
Anti dependence
(i) -------------- = x
(j) X : --------------
then i and j are anti – dependence
Hence I2 and I4 are anti-dependence
⇒ Anti-dependence create stall in pipelineCorrect Option: D
(I1) R1 ← R2 + R3
(I2) R7 ← R1 × R3
(I3) R4 ← R1 – R5
(I4) R3 ← R2 + R4
(I5) R7 ← R8 × R9
Anti dependence
(i) -------------- = x
(j) X : --------------
then i and j are anti – dependence
Hence I2 and I4 are anti-dependence
⇒ Anti-dependence create stall in pipeline
- Consider the sequence of machine instructions given below.
MUL R5, R0, R1 DIV R6, R2, R3 ADD R7, R5, R6 SUB R8, R7, R4
In the above sequence, R0 to R8 are general purpose registers. In the instruction shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write Back the result (WB). The IF, OF and WB stages take 1 clock cycle each for any instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is _________.
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I ⇒ Instruction Fetch and Decode
O ⇒ Operand Fetch
P ⇒ Perform operation
W ⇒ write back the result
Correct Option: B
I ⇒ Instruction Fetch and Decode
O ⇒ Operand Fetch
P ⇒ Perform operation
W ⇒ write back the result
