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Consider a two-level cache hierarchy with LI and L2 caches. An application incurs 1.4 memory accesses per instruction on average. For this application, the miss rate of L1 cache is 0.1; the L2 cache experiences, on average. 7 misses per 1000 instructions. The miss rate of L2 expressed correct to two decimal places is________.
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- 0.05
- 0.005
- 1.05
- 1.0015
Correct Option: A
As given that, an application incurs 1.4 memory accesses per instruction.
So, the Number of memory Accesses in 1000 instructions is
= 1.4 × 1000 = 1400.
Number of Misses in L2 cache
| = | |
| Number of Memory Accesses |
| = | = 0.005 | |
| 1400 (Memory Accesses) |
| Miss rate L2 = | ||
| Miss in L1 |
∴ (given, Miss rate of L1 cache is 0.1)
| So , L2 = | ||
| 0.1 |
Miss in L2 = 0.05
