A 5 stage pipelined CPU has the following sequence of stages
IF : Instruction fetch from instruction memory
RD : Instruction decode and register read
EX: Execute: ALU operations for data and address computation
MA : Data memory access : for write access, the register read at RD stage is used
WB : Register write back
Consider the following sequence of instructions :
I₁ : L R₀ loc 1; R₀ < = M [loc1]
I₂ : A R₀ ; R₀ ; R₀ < = R₀ + R₀
I₃ : S R₂; R₀ ; R₂ < = R₂ – R₀
Let each state takes on clock cycle.
What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I₁ ?