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Computer organization and architecture miscellaneous

Computer Organization and Architecture

  1. Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1 : Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
    P2 : Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
    P3 : Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
    P4 : Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
    Which processor has the highest peak clock frequency ?
    1. P1
    2. P2
    3. P3
    4. P4
Correct Option: C

Frequency ∝
1
clock period

Clock period = maximum stage delay + overhead
P1 : CP = Max (1, 2, 2, 1) = 2 ns
P2 : CP = Max (1, 1.5, 1.5, 1.5) = 1.5 ns
P3 : CP = Max (0.5, 1, 1, 0.6, 1) = 1 ns
P4 : CP = Max (0.5, 0.5, 1, 1, 1, 1) = 1.1 ns
∵ CP of P3 is less, it has highest frequency
Frequency 1 P3 =
1
= 1 GHz
1 ns



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