A 5-stage pipelined processor has Instruction Fetch (IF),

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A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of the instructions ?

Instruction	Meaning of instruction
I₀ : MUL R₂, R₀ , R₁	R₂ → R₀ * R₁
I₁ : DIV R₅, R₃, R₄	R₅ → R₃ / R₄
I₂ : ADD R₂ , R₅, R₂	R₂ → R₅ + R₂
I₃ : SUB R₅, R₂, R₆	R₅ → R₂ – R₆

1. 13
2. 15
3. 17
4. 19

Correct Option: B

As per the given, the instructions are arranged accordingly to their meanings. We get the following :

Here, we can see that the last operation (Write Operand) comes at the 15th clock cycle so it takes 15 clock cycles to execute given sequence of instructions.