F1 = A B
F2 = AB
X = F1F2
= [(A B) (A B)]′
= (A B)′ ( A B)′
= A + B + A + B
= 1
i.e., inhibit gate, because it does not depend upon the any value of input. Hence alternative (C) is the correct answer.

Correct Option: C

F1 = A B
F2 = AB
X = F1F2
= [(A B) (A B)]′
= (A B)′ ( A B)′
= A + B + A + B
= 1
i.e., inhibit gate, because it does not depend upon the any value of input. Hence alternative (C) is the correct answer.

Bubble an input of NAND gate means A and B

Y = A B
Y = A B (By Demorgans theorem)
= A + B
This means that Negative logic NAND gate is equivalent to OR gate
Hence alternative (B) is the correct answer.

Correct Option: B

Bubble an input of NAND gate means A and B

Y = A B
Y = A B (By Demorgans theorem)
= A + B
This means that Negative logic NAND gate is equivalent to OR gate
Hence alternative (B) is the correct answer.

Hence alternative (C) is the correct answer.

Correct Option: C

Hence alternative (C) is the correct answer.

3 × (8)³ + 7 × (8)² + 5 × 8¹ + 3 × 8º means 512, 64, 8 and 1 can be written as power of 8. The proceeding number is translatable to an octal number (3 7 5 3)₈ = (011 111 101 011)₂ Number of 1 = 9. Hence alternative (B) is the correct answer.

Correct Option: B

3 × (8)³ + 7 × (8)² + 5 × 8¹ + 3 × 8º means 512, 64, 8 and 1 can be written as power of 8. The proceeding number is translatable to an octal number (3 7 5 3)₈ = (011 111 101 011)₂ Number of 1 = 9. Hence alternative (B) is the correct answer.

CMOS: Because in CMOS circuit one transistor is always off, the quiescent power consumption is product of supply voltage and leakage current and is typically very low in microwatt range (μW).

Correct Option: C

CMOS: Because in CMOS circuit one transistor is always off, the quiescent power consumption is product of supply voltage and leakage current and is typically very low in microwatt range (μW).