Advanced Microprocessors

Advanced Microprocessors

Easy Questions

Microprocessor

8085 Microprocessors
Advanced Microprocessors
  1. The divide by N counter is shown in figure. If initially Q0 = 1, Q.1 = 1, Q2 = 0. What is a value of N?








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    Given circuit arrangement

    From given circuit arrangement, we get

    i.e., After first CLK we get 2 → 1 → 4 again and again. Thus we can conclude that the given arrangement is known as Mod–3 counter. Hence alternative (D) is the correct choice.

    Correct Option: D

    Given circuit arrangement

    From given circuit arrangement, we get

    i.e., After first CLK we get 2 → 1 → 4 again and again. Thus we can conclude that the given arrangement is known as Mod–3 counter. Hence alternative (D) is the correct choice.

  1. A certain JK flip-flop has tpd = 12·5 ns. The largest MOD counter that can be constructed from these flip-flops and still operate upto 10 MHz is—








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    Clock period =
    1
    		 = 100ns
    10 × 106

    ∴
    Number of flip-flop =
    100(ns)
    		 = 8
    12.5(ns)

    ∴ Maximum MOD counter = 256 ∴ (28 = 256)

    Correct Option: C

    Clock period =
    1
    		 = 100ns
    10 × 106

    ∴
    Number of flip-flop =
    100(ns)
    		 = 8
    12.5(ns)

    ∴ Maximum MOD counter = 256 ∴ (28 = 256)

  1. Initially Q0 = Q1 = 0. What will be the logic states of Q0and Q1 immediately after 777th clock pulse for the figure shown below—








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    This is Johnson counter as Q is feedback to input. This means it is a down counter. Number of state = 2n = 4

    So, After 776th clk pulse → State is 00, as
    777
    		 = 194
    4

    and 1 remainder. Hence, at 777th clk pulse state is 10.

    Correct Option: B

    This is Johnson counter as Q is feedback to input. This means it is a down counter. Number of state = 2n = 4

    So, After 776th clk pulse → State is 00, as
    777
    		 = 194
    4

    and 1 remainder. Hence, at 777th clk pulse state is 10.

  1. A sequential circuit using D flip-flop and logic gates is shown where X and Y are inputs and Z is output. The circuit is—








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    For D to JK conversion
    Qn + 1 = JQ + KQ …(i)
    But according to the given figure
    Z= XQ + YQ …(ii)
    comparing eqn. (i) and (ii), we get
    ⇒ X = K and Y = J

    Hence alternative (D) is the correct answer.

    Correct Option: D

    For D to JK conversion
    Qn + 1 = JQ + KQ …(i)
    But according to the given figure
    Z= XQ + YQ …(ii)
    comparing eqn. (i) and (ii), we get
    ⇒ X = K and Y = J

    Hence alternative (D) is the correct answer.

  1. Figure shows the internal schematic of TTL IC, for the input shown, output Y is—








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    When inputs are floating, assume floating input/ inputs should be equal to 1. So, Y = 1. AB = AB

    Correct Option: D

    When inputs are floating, assume floating input/ inputs should be equal to 1. So, Y = 1. AB = AB