246. The supply voltage permissible for CMOS devices is—

1. 1. + 5 V

   
   
   

   2. – 5 V

   
   
   

   3. 3 to 15 V

   
   
   

   4. + 12 V

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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247. In ECL negative supply voltage is used because of—

1. 1. reduction in noise at the output means increase in CMRR

   
   
   

   2. saving in power

   
   
   

   3. eace of wired-OR operation

   
   
   

   4. increase speed

   
   
   

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1. View Hint View Answer Discuss in Forum

   As we know that CMRR is given by
   

   CMRR =	Ad
   	Ac

   
   where, A_d = differential mode gain
   A_c = common mode gain
   A_d = V₁ – V₂
   V₁ = input voltage at inverting terminal
   

   Ac =	V1 +V2
   	2

   
   V₂ = input voltage at non-inverting terminal.
   Since we require high CMRR (i.e., CMRR → ∞), which is possible with low Ac (i.e., as Ac → 0), which is possible when V₁ and V₂ must be of opposite sign. This is the reason why we use negative supply voltage in ECL logic circuits.

   Correct Option: A

   As we know that CMRR is given by
   

   CMRR =	Ad
   	Ac

   
   where, A_d = differential mode gain
   A_c = common mode gain
   A_d = V₁ – V₂
   V₁ = input voltage at inverting terminal
   

   Ac =	V1 +V2
   	2

   
   V₂ = input voltage at non-inverting terminal.
   Since we require high CMRR (i.e., CMRR → ∞), which is possible with low Ac (i.e., as Ac → 0), which is possible when V₁ and V₂ must be of opposite sign. This is the reason why we use negative supply voltage in ECL logic circuits.

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248. CMOS logic consists of—

1. 1. only n-channel MOS devices

   
   
   

   2. only p-channel MOS devices

   
   
   

   3. equal number of n-channel and p-channel MOS devices

   
   
   

   4. None of these

   
   
   

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1. View Hint View Answer Discuss in Forum

   CMOS logic consists of equal no. of p-channel and n-channel devices.

   Correct Option: C

   CMOS logic consists of equal no. of p-channel and n-channel devices.

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249. Match each of the items a, b and c on the left with an approximate item on the right—
     

     (a) A shift register can be used	(1) for code conversion
     (b) A multiplexer can be used	(2) to generate memory chip to select
     (c) A decoder can be used	(3) for parallel-to-serial conversion
     	(4) as a many to one switch
     	(5) for analog to digital conversion

1. 1. (a) (b) (c)
        1   2   3

   
   
   

   2. (a) (b) (c)
        3   4   2

   
   
   

   3. (a) (b) (c)
        5  4   2

   
   
   

   4. (a) (b) (c)
        1  3  5

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: B

   NA

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250. For a MOD-12 counter, the Flip-Flop has a tpd = 60 ns. The NAND gate has a tpd of 25 ns. The maximum clock frequency is given by—

1. 1. 37·74 MHz

   
   
   

   2. 377·4 MHz

   
   
   

   3. 3·774 MHz

   
   
   

   4. None of these
      

   
   
   

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1. View Hint View Answer Discuss in Forum

   We know that Maximum frequency is given by
   

   fmax ≤	1
   	ts + n tPd

   
   where, n = no. of flip-flop
   t_s = propagation delay of gate
   t _Pd = propagation delay of flip-flop.
   For Mod-12 counter we require 4 flip-flop
   

   fmax ≤	1
   	(25 × 10−9 + 4 × 60 × 10−9)

   
   or f_max ≤ 3·774 MHz
   So, maximum frequency = 3·774 MHz
   Hence alternative (C) is the correct answer

   Correct Option: C

   We know that Maximum frequency is given by
   

   fmax ≤	1
   	ts + n tPd

   
   where, n = no. of flip-flop
   t_s = propagation delay of gate
   t _Pd = propagation delay of flip-flop.
   For Mod-12 counter we require 4 flip-flop
   

   fmax ≤	1
   	(25 × 10−9 + 4 × 60 × 10−9)

   
   or f_max ≤ 3·774 MHz
   So, maximum frequency = 3·774 MHz
   Hence alternative (C) is the correct answer

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