Because switching time of logic circuit in ECL is improved by estabilising one of the two states in active region instead of saturation region of transistor. The other state remains in cut-off region. This eliminates the problem of storage time and hence ECL is extremely fast with propagation delay time of 1ns (approx).

Correct Option: B

Because switching time of logic circuit in ECL is improved by estabilising one of the two states in active region instead of saturation region of transistor. The other state remains in cut-off region. This eliminates the problem of storage time and hence ECL is extremely fast with propagation delay time of 1ns (approx).

Bubble an input of NAND gate means A and B

Y = A B
Y = A B (By Demorgans theorem)
= A + B
This means that Negative logic NAND gate is equivalent to OR gate
Hence alternative (B) is the correct answer.

Correct Option: B

Bubble an input of NAND gate means A and B

Y = A B
Y = A B (By Demorgans theorem)
= A + B
This means that Negative logic NAND gate is equivalent to OR gate
Hence alternative (B) is the correct answer.

Hence alternative (C) is the correct answer.

Correct Option: C

Hence alternative (C) is the correct answer.

16) 205 (12 → C
     192
     13 → D
So, (205)₁₀ = (CD)₁₆ = (x)₁₆
Therefore, x = CD.

Correct Option: A

16) 205 (12 → C
     192
     13 → D
So, (205)₁₀ = (CD)₁₆ = (x)₁₆
Therefore, x = CD.

F1 = A B
F2 = AB
X = F1F2
= [(A B) (A B)]′
= (A B)′ ( A B)′
= A + B + A + B
= 1
i.e., inhibit gate, because it does not depend upon the any value of input. Hence alternative (C) is the correct answer.

Correct Option: C

F1 = A B
F2 = AB
X = F1F2
= [(A B) (A B)]′
= (A B)′ ( A B)′
= A + B + A + B
= 1
i.e., inhibit gate, because it does not depend upon the any value of input. Hence alternative (C) is the correct answer.