216. A counter that has a modulus of 64 should use a minimum of—
     

1. 1. 6 flip-flops
      

   
   
   

   2. 6 J-K type flip-flops
      

   
   
   

   3. 6 D flip-flops
      

   
   
   

   4. 64 flip-flops

   
   
   

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1. View Hint View Answer Discuss in Forum

   A counter that has a modulus of 64 should use a minimum of 6 flip-flops.
   We know that
   2^n-1 < N ≤ 2ⁿ
   where,
   N = No. of states or modulus
   n = No. of flip-flops
   Therefore,
   64 ≤ 2ⁿ
   Gives;
   n = 6

   Correct Option: A

   A counter that has a modulus of 64 should use a minimum of 6 flip-flops.
   We know that
   2^n-1 < N ≤ 2ⁿ
   where,
   N = No. of states or modulus
   n = No. of flip-flops
   Therefore,
   64 ≤ 2ⁿ
   Gives;
   n = 6

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217. A 10 kHz clock signal having a duty cycle of 25% is used to clock a three-bit binary ripple counter. What will be the frequency and duty cycle of the true output of the MSB flip-flop?
     

1. 1. 1.25 kHz, 25%
      

   
   
   

   2. 1.25 kHz, 50%
      

   
   
   

   3. 3.33 kHz, 25%
      

   
   
   

   4. 3.33 kHz, 50%

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: B

   NA

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218. All BCD counters—
     

1. 1. Are decade counters because all decade counters are BCD counters
      

   
   
   

   2. Are not decade counter
      

   
   
   

   3. Have a modulus of 10
      

   
   
   

   4. Are constructed with only present table D flip-flops
      

   
   
   

   5. Both (C) and (D) are correct
      

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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219. In any asynchronous counter—
     

1. 1. All flip-flops change state at the same time
      

   
   
   

   2. Only D flip-flops are used
      

   
   
   

   3. The counter responds to negative going clock edges
      

   
   
   

   4. Each flip-flop output serves as clock input to the next flip-flop
      

   
   
   

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1. View Hint View Answer Discuss in Forum

   In any asynchronous counter each flip-flop output serves as clock input to the next flip-flop.

   Correct Option: D

   In any asynchronous counter each flip-flop output serves as clock input to the next flip-flop.

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220. A four-bit binary UP-DOWN counter is initially reset to 0000. The UP/DOWN mode select terminal designated as U/D on the pin connection diagram of the IC is tied to logic HIGH level. What would be the counter’s output state at the end of the first clock pulse?
     

1. 1. 0001
      

   
   
   

   2. 1000
      

   
   
   

   3. 1111
      

   
   
   

   4. 0000
      

   
   
   

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1. View Hint View Answer Discuss in Forum

   Since if will work in down mode. Therefore, output after first clock pulse will be 1111.

   Correct Option: C

   Since if will work in down mode. Therefore, output after first clock pulse will be 1111.

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