116. In what type of shift register do we have access to only the leftmost and rightmost flip-flops—
     

1. 1. Serial-in/serial-out shift register
      

   
   
   

   2. Serial-in/parallel-output shift register
      

   
   
   

   3. Parallel-in/serial-out shift register
      

   
   
   

   4. Parallel-in/parallel-out shift register

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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117. Mark the false statement—
     

1. 1. Ring counter is a synchronous counter
      

   
   
   

   2. Johnson counter is a synchronous counter
      

   
   
   

   3. The output of a ring counter is always a square wave
      

   
   
   

   4. The decoding circuitry for a Johnson counter is simpler than that of a binary counter

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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118. A decoding gate required to produce a LOW output when a MOD-64 counter is at the count of 27 is—

1. 1. 6-input AND () A‚ B‚ C‚ D‚ E‚ F

   
   
   

   2. 6-input NAND () A‚ B‚ C‚ D‚ E‚ F

   
   
   

   3. 6-input AND () A‚ B‚ C‚ D‚ E‚ F

   
   
   

   4. 6-input NAND () A‚ B‚ C‚ D‚ E‚ F

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: B

   NA

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119. A counter that has a modulus of 64 should use a minimum of—
     

1. 1. 6 flip-flops
      

   
   
   

   2. 6 J-K type flip-flops
      

   
   
   

   3. 6 D flip-flops
      

   
   
   

   4. 64 flip-flops

   
   
   

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1. View Hint View Answer Discuss in Forum

   A counter that has a modulus of 64 should use a minimum of 6 flip-flops.
   We know that
   2^n-1 < N ≤ 2ⁿ
   where,
   N = No. of states or modulus
   n = No. of flip-flops
   Therefore,
   64 ≤ 2ⁿ
   Gives;
   n = 6

   Correct Option: A

   A counter that has a modulus of 64 should use a minimum of 6 flip-flops.
   We know that
   2^n-1 < N ≤ 2ⁿ
   where,
   N = No. of states or modulus
   n = No. of flip-flops
   Therefore,
   64 ≤ 2ⁿ
   Gives;
   n = 6

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120. A 10 kHz clock signal having a duty cycle of 25% is used to clock a three-bit binary ripple counter. What will be the frequency and duty cycle of the true output of the MSB flip-flop?
     

1. 1. 1.25 kHz, 25%
      

   
   
   

   2. 1.25 kHz, 50%
      

   
   
   

   3. 3.33 kHz, 25%
      

   
   
   

   4. 3.33 kHz, 50%

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: B

   NA

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