To add two m-bit numbers, the required no. of half adder is 2m–1.

Correct Option: A

To add two m-bit numbers, the required no. of half adder is 2m–1.

To get X = 1 output of EX-OR gate and EX - NOR gate must be 1 and in order to make
Y₁ = 1 → A should be 0 and B should be 1
Y₂ = 1 → C should be 1 and B should be 1. So, to
get X = 1 the condition (0, 1, 1) is correct.

Correct Option: D

To get X = 1 output of EX-OR gate and EX - NOR gate must be 1 and in order to make
Y₁ = 1 → A should be 0 and B should be 1
Y₂ = 1 → C should be 1 and B should be 1. So, to
get X = 1 the condition (0, 1, 1) is correct.

Given, F = (A + B) ( A + C)
or F = AA + AB + BC + AC
or F = AB + BC + AC
To minimize this function, it can be solved easily by using K-map given below:
From K-map, we get F = AB + AC

Correct Option: C

Given, F = (A + B) ( A + C)
or F = AA + AB + BC + AC
or F = AB + BC + AC
To minimize this function, it can be solved easily by using K-map given below:
From K-map, we get F = AB + AC

Given, F = A + AB + ABC
or F = A (1 + B) + ABC
or F = A + ABC [since 1 + B = 1]
or F = A (1 + BC)
or F = A [since 1 + BC = 1)
Therefore, minimum number of NAND gate required to implement F = A is zero.

Correct Option: A

Given, F = A + AB + ABC
or F = A (1 + B) + ABC
or F = A + ABC [since 1 + B = 1]
or F = A (1 + BC)
or F = A [since 1 + BC = 1)
Therefore, minimum number of NAND gate required to implement F = A is zero.

When signed numbers are used in binary arithmetic, then 2’S complement notation would have unique representation for zero.

Correct Option: C

When signed numbers are used in binary arithmetic, then 2’S complement notation would have unique representation for zero.