31. A 4 bit modulo-6 ripple counter uses JK flip-flop. If propagation delay of each FF is 50 ns, then maximum clock frequency that can be used is equal to _________MHz

1. 1. 1

   
   
   

   2. 3

   
   
   

   3. 7

   
   
   

   4. 5

   
   
   

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1. View Hint View Answer Discuss in Forum

   4 bit uses 4 FF
   Total delay N_td = 4 × 50 ns = 200 × 10^–9
   

   f =	1	= 5 MHz
   	200 × 10-9

   Correct Option: D

   4 bit uses 4 FF
   Total delay N_td = 4 × 50 ns = 200 × 10^–9
   

   f =	1	= 5 MHz
   	200 × 10-9

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32. The number of comparator sin a parallel conversion type 8-bit A to D converter is ____________.

1. 1. 256

   
   
   

   2. 255

   
   
   

   3. 245

   
   
   

   4. 256

   
   
   

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1. View Hint View Answer Discuss in Forum

   Number of comparators = 2^N – 1 = 2⁸ – 1 = 255

   Correct Option: B

   Number of comparators = 2^N – 1 = 2⁸ – 1 = 255

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33. ƒ(A,B,C,D) = πm (0,1,3,4,5,7,9,11,12,13,14,15) is a maxterm representation of a Boolean function ƒ(A,B,C,D) where A is the MSB and D is the LSB. The equivalent minimized representation of this function is

1. 1. (A + C + D)(A + B + D)

   
   
   

   2. ACD + ABD

   
   
   

   3. ACD + ABCD + ABCD

   
   
   

   4. (B + C + D)(A + B + C + D)(A + B + C + D)

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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34. In the following sequential circuit, the initial state (before the first clock pulse) of the circuit is Q₁Q₀ = 00. The state (Q₁Q₀), immediately after the 333^rd clock pulse is
    

1. 1. 00

   
   
   

   2. 01

   
   
   

   3. 10

   
   
   

   4. 11

   
   
   

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1. View Hint View Answer Discuss in Forum

   
   If the counter is Johnson (MOD-4) counter. Divide 333 by 4, so it will complete 83 cycle and remainder clock is 1, at the completion of cycles output’s in at Q₁Q₀ = 00 so, next at 333^rd clock pulse output is at Q₁Q₀ = 01.

   Correct Option: B

   
   If the counter is Johnson (MOD-4) counter. Divide 333 by 4, so it will complete 83 cycle and remainder clock is 1, at the completion of cycles output’s in at Q₁Q₀ = 00 so, next at 333^rd clock pulse output is at Q₁Q₀ = 01.

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35. A dual trace oscilloscope is set to operate in the ALTernate mode. The control input of the multiplexer used in the y-circuit is fed with a signal having a frequency equal to

1. 1. the highest frequency that the multiplexer can operate properly

   
   
   

   2. twice the frequency of the time base (sweep) oscillator

   
   
   

   3. the frequency of the time base (sweep) oscillator

   
   
   

   4. half the frequency of the time base (sweep) oscillator

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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