61. The output of the circuit will be
    
    

1. 1. ABCD + ABCD + ABCD + ABC D D

   
   
   

   2. ABCD + ABCD + ABCD + ABCD

   
   
   

   3. ABCD + ABCD + ABCD + ABCD

   
   
   

   4. ABCD + ABCD + ABCD + ABCD

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: D

   NA

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62. The type of gate shown in the given figure is
    

1. 1. OR

   
   
   

   2. NOR

   
   
   

   3. NAND

   
   
   

   4. EX-OR

   
   
   

   5. EX-NOR

   
   
   

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   NA

   Correct Option: D

   NA

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63. Schmitt trigger is shown in the figure. The upper and lower threshold voltage are respectively
    
    

1. 1. 2 V, – 4 V

   
   
   

   2. 2 V, – 2 V

   
   
   

   3. 4 V, – 4 V

   
   
   

   4. 4 V, – 2 V

   
   
   

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1. View Hint View Answer Discuss in Forum

   Upper crossover voltage when V₀ = + 10 V At upper threshold point
   

   5

   (10) =

   5

   (2) +

   20

   VTL

   5 + 20

   10 + 20

   10 + 20

   
   

   ⇒	2	VTH = 2 -	2	⇒ VTH = 2V
   	3		3

   
   Lower crossover voltage when V₀ = – 10 V
   

   5

   (-10) =

   10

   (2) =

   20

   VTL

   5 + 20

   10 + 20

   10 + 20

   
   ⇒ V_TL = – 4V

   Correct Option: C

   Upper crossover voltage when V₀ = + 10 V At upper threshold point
   

   5

   (10) =

   5

   (2) +

   20

   VTL

   5 + 20

   10 + 20

   10 + 20

   
   

   ⇒	2	VTH = 2 -	2	⇒ VTH = 2V
   	3		3

   
   Lower crossover voltage when V₀ = – 10 V
   

   5

   (-10) =

   10

   (2) =

   20

   VTL

   5 + 20

   10 + 20

   10 + 20

   
   ⇒ V_TL = – 4V

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64. A switch-tail ring counter is made by using a single D-FF. The resulting ciruit is

1. 1. SR flip-flop

   
   
   

   2. JK flip-flop

   
   
   

   3. D – FF

   
   
   

   4. T – FF

   
   
   

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1. View Hint View Answer Discuss in Forum

   In a switch– tail ring counter, using D-FF, the complementary output Q is connected to D input for a single D-FF it becomes a T-FF.
   

   Correct Option: D

   In a switch– tail ring counter, using D-FF, the complementary output Q is connected to D input for a single D-FF it becomes a T-FF.
   

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65. A 4– bit modulo– 16 ripple counter used JK flipflop. If progression delay of each FF is 50 ms, then maximum clock frequency is equal to
    

1. 1. 20 MHz

   
   
   

   2. 10 MHz

   
   
   

   3. 5 MHz

   
   
   

   4. 4 MHz

   
   
   

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1. View Hint View Answer Discuss in Forum

   ƒmax =	1	=	1
   	N:Td		4 × 50 × 10-12

   
   = 5 MHZ.

   Correct Option: C

   ƒmax =	1	=	1
   	N:Td		4 × 50 × 10-12

   
   = 5 MHZ.

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