51. The output of the 4 × 1 multiplexer shown in the figure, is
    

1. 1. X + Y

   
   
   

   2. X + Y

   
   
   

   3. XY + X

   
   
   

   4. XY

   
   
   

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1. View Hint View Answer Discuss in Forum

   Z = XY + XY + XY,
   Z = X + Y

   Correct Option: A

   Z = XY + XY + XY,
   Z = X + Y

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52. The 8-to-1 multiplexer shown in the figure, realize which of the following Boolean expression?
    

1. 1. wxz + wxz + wyz + xyz

   
   
   

   2. wxz + wyz + wyz + wxy

   
   
   

   3. wxz + wyz + wyz + wxz

   
   
   

   4. MUX is not enable

   
   
   

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1. View Hint View Answer Discuss in Forum

   Let z = 0
   Then ƒ = wxy + wxy + wxy + wxy = wx + wy
   If we put z = 0 in given option, then
   (a) = wx + xy (b) = wy + wxy (c) = wx + wy
   Since MUX is enable.

   Correct Option: C

   Let z = 0
   Then ƒ = wxy + wxy + wxy + wxy = wx + wy
   If we put z = 0 in given option, then
   (a) = wx + xy (b) = wy + wxy (c) = wx + wy
   Since MUX is enable.

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53. A retriggerable monoshot is one which

1. 1. can be triggered only once

   
   
   

   2. has two quasi-stable states

   
   
   

   3. cannot be triggered until full pulse has been

   
   
   

   4. is capable of being triggered while the output is being

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: D

   NA

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54. A 4-bit-synchronous counter uses flip-flops with pr opagation delay time of 25 ns each. The maximum possible time required for change of state will be

1. 1. 25 ns

   
   
   

   2. 50 ns

   
   
   

   3. 75 ns

   
   
   

   4. 100 ns

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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55. A full-adder can be implemented with half-adders and OR gates. A 4-bit parallel full adder without any initial carry requires

1. 1. 8 half-adders,4-OR gates

   
   
   

   2. 8 half-adders, 3-OR gates

   
   
   

   3. 7 half-adders, 4-OR gates

   
   
   

   4. 7 half-adders, 3-OR gates

   
   
   

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1. View Hint View Answer Discuss in Forum

   The circuit of a 4-bit full adder using half adders and OR gates is shown in the figure
   From the figure, it is apparent that 4-bit full adder required seven half adders and 3-OR gates.
   

   Correct Option: D

   The circuit of a 4-bit full adder using half adders and OR gates is shown in the figure
   From the figure, it is apparent that 4-bit full adder required seven half adders and 3-OR gates.
   

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