66. Metastability in D-Flip Flop occurs when
    

1. 1. set up time of input data is not met

   
   
   

   2. clock period is too large

   
   
   

   3. set and reset are active simultaneously

   
   
   

   4. D and Q pins are shortened.

   
   
   

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   NA

   Correct Option: A

   NA

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67. In a sequential circuit, the outputs at anyinstant of time depends

1. 1. only on the inputs present at that instant of time

   
   
   

   2. on past outputs as well as present inputs

   
   
   

   3. only on the past inputs

   
   
   

   4. only on the present outputs

   
   
   

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   NA

   Correct Option: B

   NA

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68. For a flip-flop formed from two NAND gates as shown in the given figure, the unusable state corresponds to
    

1. 1. X = 0, Y = 0

   
   
   

   2. X = 0, Y = 1

   
   
   

   3. X = 1, Y = 0

   
   
   

   4. X = 1, Y = 1

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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69. A pulse train with a frequency of 1 MHz is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage is
    

1. 1. 100 n sec

   
   
   

   2. 50 n sec

   
   
   

   3. 20 n sec

   
   
   

   4. 10 n sec

   
   
   

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1. View Hint View Answer Discuss in Forum

   Maximum frequency of 1 MHz corresponds to minimum time = 1/1 × 10⁶ = 1 microsecond = 100 nanoseconds.

   Correct Option: A

   Maximum frequency of 1 MHz corresponds to minimum time = 1/1 × 10⁶ = 1 microsecond = 100 nanoseconds.

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70. Four memory chips of 16 × 4 size have their address buses connected together. This system will be of size

1. 1. 64 × 4

   
   
   

   2. 32 × 8

   
   
   

   3. 16 × 16

   
   
   

   4. 256 × 1

   
   
   

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1. View Hint View Answer Discuss in Forum

   Since all chip has same address, the capacity of word will be increased.
   

   Correct Option: C

   Since all chip has same address, the capacity of word will be increased.
   

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