46. The logic realized by the circuit shown in the figure below, is
    

1. 1. F = A ⊙ C

   
   
   

   2. F = A ⊕ C

   
   
   

   3. F = B ⊙ C

   
   
   

   4. F = B ⊕ C

   
   
   

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1. View Hint View Answer Discuss in Forum

   F = A B C + A B C + A B C
   = A C (B + B) + A C (B + B)
   = A C + A C
   = A ⊕ C

   Correct Option: B

   F = A B C + A B C + A B C
   = A C (B + B) + A C (B + B)
   = A C + A C
   = A ⊕ C

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47. In time devision multiplexing
    

1. 1. time is doubled between bits of a byte

   
   
   

   2. time slicing at CPU level takes place

   
   
   

   3. total time available in the channel is divided bet ween sever al user s and each user s is allotted a time slice

   
   
   

   4. none of these

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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48. The output ƒ of the 4-to-1 MUX shown in the given figure is
    
    

1. 1. xy + x

   
   
   

   2. x + y

   
   
   

   3. x + y

   
   
   

   4. xy + x

   
   
   

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1. View Hint View Answer Discuss in Forum

   

   Correct Option: B

   

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49. The output F of the multiplexer circuit shown in the given figure can be represented by
    
    

1. 1. AB + BC + CA + BC

   
   
   

   2. A ⊕ B ⊕ C

   
   
   

   3. A ⊕ B

   
   
   

   4. ABC + AB C + A BC

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: D

   NA

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50. A sequential multiplexer is connected as shown in the figure. Each time the multiplexer receivers the clock, it switches to the next cannel (from 6 it goes to 1) if input signals are

1. 1. 5 cos (2π (4 × 10³t)

   
   
   

   2. 2 cos 2π (3.8 × 10³t)

   
   
   

   3. 6 cos 2π (2.2 × 10³t)

   
   
   

   4. 4 cos 2π (17 × 10³t)

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: D

   NA

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