31. A pulse train can be delayed by a finite number periods usings of clock
    

1. 1. a serial – in – serial shift register

   
   
   

   2. a serial – in – parallel – out shift register

   
   
   

   3. a parallel – in serial – out shift register

   
   
   

   4. a serial – in parallel – out shift register

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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32. The initial contents of the 4-bit serial-in-parallelout, right-shift. Shift Register shown in the given figure is 0110. After three clock pulses are applied, contents of the Shift Register will be Clock Serial in
    
    

1. 1. 0000

   
   
   

   2. 0101

   
   
   

   3. 1010

   
   
   

   4. 1111

   
   
   

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1. View Hint View Answer Discuss in Forum

   4 bit SIPO
   Pulse 1 XOR (1, 0) = 1 1011
   2 XOR (1, 1) = 0 0101
   3 XOR (0,1) = 1 1010
   The contents will be 1010.
   

   Correct Option: C

   4 bit SIPO
   Pulse 1 XOR (1, 0) = 1 1011
   2 XOR (1, 1) = 0 0101
   3 XOR (0,1) = 1 1010
   The contents will be 1010.
   

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33. A mod-2 counter followed by a mod-5 counter is
    

1. 1. same as a mode-5 counter followed by a mod- 2 counter

   
   
   

   2. a decade counter

   
   
   

   3. a mod-7 counter

   
   
   

   4. none of these

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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34. The block diagram shown below represents
    

1. 1. modulo – 3 ripple counter

   
   
   

   2. modulo – 5 ripple counter

   
   
   

   3. modulo – 7 ripple counter

   
   
   

   4. modulo – 7 synchronous counter

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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35. The output Q_n of a J-K flip-flop is zero. It change to 1 when a clock pulse is applied. The input J_n and K_n are respectively
    

1. 1. 1 and X

   
   
   

   2. 0 and X

   
   
   

   3. X and 0

   
   
   

   4. X and 1

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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