Digital circuits miscellaneous
- A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1 μsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/ H circuit is 5V. The leakage current of the S/H circuit should be less than _____________μA
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I = Q = 0.5/100 × Q t t = 0.005 × CV = 0.5 × 10-10 × 5 10-6 10-6
= 25 × 10-7 = 2.5 μA.Correct Option: D
I = Q = 0.5/100 × Q t t = 0.005 × CV = 0.5 × 10-10 × 5 10-6 10-6
= 25 × 10-7 = 2.5 μA.
- A 5 bit D/A converter has a current output for a digital input of 10100. If an output current of 10 m A is produced, what will Iout be for a digital input of 11101?
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The digital input 10100 is the binary equivalent of 2010.
Since, Iout = 10mA, for this case proportionating factor is 0.5
i.e. I out = 0.5 × binary value.
Thus, binary input 11101 is equivalent ot 2910,
∴ Iout = 0.5 × 29 = 14.5 mA.Correct Option: C
The digital input 10100 is the binary equivalent of 2010.
Since, Iout = 10mA, for this case proportionating factor is 0.5
i.e. I out = 0.5 × binary value.
Thus, binary input 11101 is equivalent ot 2910,
∴ Iout = 0.5 × 29 = 14.5 mA.
- What overall accuracy could one reasonably expect from construction of a 10 bit A/D converter?
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A 10 bit convertor has a quantization error of
= 1 = 1 = 0.1 % 1024 210
If an analog portion can be constructed to an accuracy of 0.1%, it would seen reasonable to strive for an overall accuracy of 0.2%.Correct Option: B
A 10 bit convertor has a quantization error of
= 1 = 1 = 0.1 % 1024 210
If an analog portion can be constructed to an accuracy of 0.1%, it would seen reasonable to strive for an overall accuracy of 0.2%.
- A 10 bit A/D converter is used to digitise an analog signal in the 0 to 5 V range. The maximum peak to peak ripple voltage that can be allowed in the d.c. supply voltage is
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Smallest incremental change
= 1 = 1 210 1024 For 5v, 5 = nearly 5 mV 1024 Correct Option: D
Smallest incremental change
= 1 = 1 210 1024 For 5v, 5 = nearly 5 mV 1024
- For a MOD-12 counter, FF hasa tpd = 60 ns. NAND gate has a tpd of 25 ns. The clock frequency is
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For proper functioning, clock period should be equal to or greater than all the tpd
MOD – 12 – 4 FFs = 4 × 60 = 240 ns.
tpd = 25 ns.
∴ Total tpd = 265 ns
ƒc = 3.774 MHzCorrect Option: A
For proper functioning, clock period should be equal to or greater than all the tpd
MOD – 12 – 4 FFs = 4 × 60 = 240 ns.
tpd = 25 ns.
∴ Total tpd = 265 ns
ƒc = 3.774 MHz
