Compiler design miscellaneous


Compiler design miscellaneous

  1. Match the following :
    (P) Lexical analysis (i) Leftmost derivation
    (Q) Top down parsing (ii) Type checking
    (R) Semantic analysis (iii) Regular expressions
    (S) Runtime environments (iv) Activation records









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    NA

    Correct Option: B

    NA


  1. Match the following according to input (from the left column) to the compiler phase (in the right column) that processes it :
    (P) Syntax tree (i) Code generator
    (Q) Character stream (ii) Syntax analyzer
    (R) Intermediate (iii) Semantic analyzer representation
    (S) Token stream (iv) Lexical analyzer









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    According to the complier phase. Shown in figure below. The lexical analysis Phase Processes the character strem and generates tokens stream, these tokens are processed by syntex analysis analyzer and generate the syntex tree. these syntex tree is processed by the semantic analyzer, and generate the intermediate representation such as (3-Address code) is used for code generation process.

    Correct Option: C

    According to the complier phase. Shown in figure below. The lexical analysis Phase Processes the character strem and generates tokens stream, these tokens are processed by syntex analysis analyzer and generate the syntex tree. these syntex tree is processed by the semantic analyzer, and generate the intermediate representation such as (3-Address code) is used for code generation process.



  1. Which of the following statements is false?









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    So (a) & (c) are, true.
    An ambiguous grammar can't be LR (K)
    So option (a) is false since an unambiguous grammar has unique right most derivation & left most derivations but both are not same. Hence (a) is correct option

    Correct Option: A

    So (a) & (c) are, true.
    An ambiguous grammar can't be LR (K)
    So option (a) is false since an unambiguous grammar has unique right most derivation & left most derivations but both are not same. Hence (a) is correct option


  1. In a simplified computer, the instructions are
    OP Rj, Ri – Performs Rj OP Ri and stores the result in register Ri .
    OP m, Rj – Performs val OP Ri and stores the result in Rj. val denotes the content of memory location m.
    MOV m, Ri – Moves the content of memory location m to register Ri.
    MOV, Ri, m – Moves the content of the register Ri to memory location m.
    The computer has only two registers, and OP is either ADD or SUB. Consider the following basic block:
    t1 = a + b
    t2 = c + d
    t3 = e – t2
    t4 = t1 – t3
    Assume that all operands are initially in memory. The final value of the computation should be in memory. What is the minimum number of MOV instructions in the code generated for this basic block?









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    This how, we obtain 3 MOV instruction in the code generated for the basic block.

    Correct Option: B


    This how, we obtain 3 MOV instruction in the code generated for the basic block.



  1. Some code optimizations are carried out on the intermediate code because









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    Code optimizations are carried out on the intermediate code because program analysis is more accurte on intermediate code than on machine code.

    Correct Option: B

    Code optimizations are carried out on the intermediate code because program analysis is more accurte on intermediate code than on machine code.