16. Consider the following statements: For a Master-Slave JK flip-flop,
    1. the toggle frequency is the maximum clock frequency at which the flip-flop will toggle reliably.
    2. the data input must preceds the clock triggering edge transition time by some minimum time.
    3. the data input must remain fixed for a given time after, the clock triggering edge transition time for reliable operation.
    4. propagation delay time is equal to the rise time and fall time of the data. Which of the above statements is/are correct?

1. 1. 1, 2 and 3

   
   
   

   2. 1 and 2 only

   
   
   

   3. 2 and 3 only

   
   
   

   4. 3 and 4 only

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: B

   NA

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17. For each of the positive edge-triggered JK flip-flop used in the following figure, the propagation delay is ∆T.
    Which of the following waveforms correctly represents the output at Q1?
    
    
    

1. 1. 1
      

   
   
   

   2. 2
      

   
   
   

   3. 3
      

   
   
   

   4. 4
      

   
   
   

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   The output of flip-flop is one fourth of the CLK frequency and 2∆T is the propagation delay of 2 flip-flops.
   

   Correct Option: B

   The output of flip-flop is one fourth of the CLK frequency and 2∆T is the propagation delay of 2 flip-flops.
   

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18. The basic sequential logic building block in which the output follows the data input as long as the ENABLE input is active is—

1. 1. J-K flip-flop

   
   
   

   2. D flip-flop

   
   
   

   3. T flip-flop

   
   
   

   4. D latch

   
   
   

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   As we know that latch is level triggered while flip-flop are edge triggered. Therefore in D latch the output follows the data input as long as the ENABLE input is active.
   Hence alternative (D) is the correct choice.

   Correct Option: D

   As we know that latch is level triggered while flip-flop are edge triggered. Therefore in D latch the output follows the data input as long as the ENABLE input is active.
   Hence alternative (D) is the correct choice.

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19. If the J-input of a J-K flip-flop is treated as input and an inverter is wired between J and K inputs, the J-K flip-flop becomes—

1. 1. R-S flip-flop

   
   
   

   2. D flip-flop

   
   
   

   3. T flip-flop

   
   
   

   4. D latch

   
   
   

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1. View Hint View Answer Discuss in Forum

   The above circuit becomes D flip-flop.

   
   

   Correct Option: B

   The above circuit becomes D flip-flop.

   
   

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20. One of the following is not a synchronous input with reference to flip-flops—

1. 1. J input in a J-K flip-flop

   
   
   

   2. S input in an R-S flip-flop

   
   
   

   3. PRESET input in a J-K flip-flop

   
   
   

   4. D input in a D flip-flop

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

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