21. In a 4-bit weighted resistor D/A converter, the resistor value corresponding to LSB is 32-k ohm. The resistor value corresponding to MSB will be _________kΩ

1. 1. 1

   
   
   

   2. 2

   
   
   

   3. 3

   
   
   

   4. 4

   
   
   

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1. View Hint View Answer Discuss in Forum

   2^n–1 R = 32,
   where n = 4
   ∴ 2³R = 32
   ⇒ R = 4k -ohm

   Correct Option: D

   2^n–1 R = 32,
   where n = 4
   ∴ 2³R = 32
   ⇒ R = 4k -ohm

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22. An analog voltage is in the range of 0 to 8 V is divided in eight equal intervals for conversion to 3-bit digital output. The maximum quantization error is _________V

1. 1. 1

   
   
   

   2. 2

   
   
   

   3. 3

   
   
   

   4. 4

   
   
   

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1. View Hint View Answer Discuss in Forum

   Quantizing error = V/2^N
   = 8/2³ = 1V.

   Correct Option: A

   Quantizing error = V/2^N
   = 8/2³ = 1V.

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23. For the Schmitt trigger oscillator shown in the given figure saturation output voltage are + 10 V and – 5 V. The frequency of oscillation is ___________Hz
    

1. 1. 869

   
   
   

   2. 879

   
   
   

   3. 889

   
   
   

   4. 899

   
   
   

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1. View Hint View Answer Discuss in Forum

   Switching voltage are
   

   V+ =	10	= 5V,     V+ = -	5	= - 2.5 V
   	2		2

   
   The charging and discharging of capacitor is shown in the figure
   
   ∴ 5 = 10 + (– 2.5 – 10) e^-t₁/RC
   ⇒ e^-t₁/RC = 2/5 ⇒ t₁ = RC ln 2.5
   ∴ – 2.5 = – 5 + (5 – (– 5)) e^-t₁/RC
   ∴ e^-t₁/RC = 1/4
   ⇒ t₂ = RC ln 4,
   T = t₁ + t₂ = RC ln 2.5 + RC ln 4
   = RC ln 10 R
   = 50 kΩ, C = 0.01 μF
   ⇒ T = 50k × 0.01μ × ln 10 = 1.15 ms
   ƒ = 1/T = 869 Hz

   Correct Option: A

   Switching voltage are
   

   V+ =	10	= 5V,     V+ = -	5	= - 2.5 V
   	2		2

   
   The charging and discharging of capacitor is shown in the figure
   
   ∴ 5 = 10 + (– 2.5 – 10) e^-t₁/RC
   ⇒ e^-t₁/RC = 2/5 ⇒ t₁ = RC ln 2.5
   ∴ – 2.5 = – 5 + (5 – (– 5)) e^-t₁/RC
   ∴ e^-t₁/RC = 1/4
   ⇒ t₂ = RC ln 4,
   T = t₁ + t₂ = RC ln 2.5 + RC ln 4
   = RC ln 10 R
   = 50 kΩ, C = 0.01 μF
   ⇒ T = 50k × 0.01μ × ln 10 = 1.15 ms
   ƒ = 1/T = 869 Hz

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24. The switching circuit given in the figure can be expressed in binary logic notation as
    

1. 1. L = (A + B) (C + D) E

   
   
   

   2. L = AB + CD + E

   
   
   

   3. L = E + (A + B) (C + D)

   
   
   

   4. L = (AB + CD) E

   
   
   

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1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

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25. Figure given below shows four D t ype FF's connected as a shift register using an X OR gate. The initial state and 3 subsequent states for 3 clock pulses are also given.
    
    State Q_A Q_B Q_C Q_D after fourth clock pulse is
    

1. 1. 0000

   
   
   

   2. 1111

   
   
   

   3. 1001

   
   
   

   4. 1000

   
   
   

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1. View Hint View Answer Discuss in Forum

   Naming the FFs as 1 to 4 from Left to Right after the 3^rd clock pulse FF3 is 0 and FF4 is 1 so that X OR output is 1 which is fed to Q_A.
   So Q_A to Q_B → 0 Q_B to Q_C → 0. Q_C → Q_D → 0
   After 4^th clock pulse 1000

   Correct Option: D

   Naming the FFs as 1 to 4 from Left to Right after the 3^rd clock pulse FF3 is 0 and FF4 is 1 so that X OR output is 1 which is fed to Q_A.
   So Q_A to Q_B → 0 Q_B to Q_C → 0. Q_C → Q_D → 0
   After 4^th clock pulse 1000

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