Figure given below shows four D t ype FF's connected as

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Figure given below shows four D t ype FF's connected as a shift register using an X OR gate. The initial state and 3 subsequent states for 3 clock pulses are also given.

State Q_A Q_B Q_C Q_D after fourth clock pulse is

1. 0000
2. 1111
3. 1001
4. 1000

Correct Option: D

Naming the FFs as 1 to 4 from Left to Right after the 3^rd clock pulse FF3 is 0 and FF4 is 1 so that X OR output is 1 which is fed to Q_A.
So Q_A to Q_B → 0 Q_B to Q_C → 0. Q_C → Q_D → 0
After 4^th clock pulse 1000