81. During a DMA transfer, the processor (check the incorrect statement)
    

1. 1. continues its normal operations

   
   
   

   2. suspends its normal operations

   
   
   

   3. needs to initiate read (write) command

   
   
   

   4. needs to check if the input/output device is ready for data transfer

   
   
   

---

1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: A

   NA

---

82. In 8085, interrupts excepts TRAP are disabled (check the incorrect statement) by
    

1. 1. a DI instruction

   
   
   

   2. a system reset

   
   
   

   3. acknowledgement of a previous interrupt

   
   
   

   4. none of these

   
   
   

---

1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: D

   NA

---

---

83. A high on RESET OUT line signifies that
    

1. 1. all the registers of the CPU are being reset

   
   
   

   2. all the registers and counters are being reset

   
   
   

   3. all the registers and counters are being reset and in addition this signal can be used to reset external support chips

   
   
   

   4. processing can begin when this signal goes high

   
   
   

---

1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

---

84. Normally a microprocessor cycles between
    

1. 1. Fetch and Halt states

   
   
   

   2. Fetch and Interrupt states

   
   
   

   3. Fetch and Execute states

   
   
   

   4. Halt and Execute states

   
   
   

---

1. View Hint View Answer Discuss in Forum

   NA

   Correct Option: C

   NA

---

---

85. In an 8085 A microprocessor based system, it is desired to increment the contents of memory location whose address is available in (D,E) register pair and store the result in same location. The sequence of instructions is
    
    
    

1. 1. XCHG
      INR M

   
   
   

   2. XCHG
      INX H

   
   
   

   3. INX D
      XCHG

   
   
   

   4. INR M
      XCHG

   
   
   

---

1. View Hint View Answer Discuss in Forum

   The address of the memory location is stored in DE register pair. But INR M command will increase the content of the memory location M. But this command will execute only on HL pair. So we have to exchange the address of Memory location in HL pair from DE pair first.

   Correct Option: A

   The address of the memory location is stored in DE register pair. But INR M command will increase the content of the memory location M. But this command will execute only on HL pair. So we have to exchange the address of Memory location in HL pair from DE pair first.

---