Let the clock cycles required for vavious operations be

Direction: Consider the following program segment for a hypothetical CPU having three user registers R₁, R₂ and R₃.

Let the clock cycles required for vavious operations be as follows: Register to/from memory transfer: 3 clock cycles
Add with both operands in register: 1 clock cycle
Instruction fetch and decode: 2 clock cycles per word
The total number of clock cycles requires to execute the program is

The clock cycles are per block so if an instruction size is 2 then it requires twice no. of clock cycles.