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Consider a three word machine instruction:
ADD A[R0], @ B
The first operand (destination) “A[R0]” uses indexed addressing mode with R0 as the index register. The second operand (source) “@B” uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is
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- 3
- 4
- 5
- 6
- 3
Correct Option: B
The given instruction can be written as:
A [R0] ← A[R0] + @B
So, 2 memory accesses for fetching operand B, 1 for A[R0] and 1 for write back into A[R0]...
Hence 4 memory accesses are required in total.
⇒ Hence option (B) is the correct answer.
Delay slots in pipeline caused due to a branch instruction 2.
