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A process uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 kbyte. Each page table entry is of size 4 byte. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows
Bit 30-31 are used to index into the first level page table
Bit 21-29 are used to index into the second level page table
Bit 12-20 are used to index into the third level page table,
and Bit 0-11 are used as offset within the page
The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively
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- 20, 20 and 20
- 24, 24 and 24
- 24, 24 and 20
- 25, 25 and 24
- 20, 20 and 20
Correct Option: D
Virtual address size = 32 bits
Physical address size = 36 bits
Physical memory size = 2^36 bytes
Page frame size = 4K bytes = 2^12 bytes
No. of bits required to access physical memory frame = 36 – 12 = 24
So in third level of page table, 24 bits are required to access an entry.
9 bits of virtual address are used to access second level page table entry and size of pages in second level is 4 bytes. So size of second level page table is (2^9)*4 = 2^11 bytes. It means there are (2^36)/(2^11) possible locations to store this page table. Therefore the second page table requires 25 bits to address it. Similarly, the third page table needs 25 bits to address it.
