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For the circuit shown below, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible Which of the following statements in true?
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- Q goes to 1 at the CLK transition and stays at 1
- Q goes to 0 at the CLK transition and stays at 0
- Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
- Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
Correct Option: C
The given circuit
From the given circuit we conclude that Q goes to 1 at the CLK transition and goes to 0 when D goes to 1.
