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Digital electronics miscellaneous

Digital Electronics

  1. We have two negative edge-triggered J-K flip-flops with active-LOW inputs J and K inputs of both the flip-flops have been permanently tied to logic ‘0’. The Q output of first flip-flop. What will be the logic status of outputs Q1 and Q2 at the end of five clock cycles if the two outputs were cleared to logic ‘0’ before start?
    1. Q1 = 1, Q2 = 0
    2. Q1 = 1, Q2 = 1
    3. Q1 = 0, Q2 = 1
    4. Q1 = 0, Q2 = 0
Correct Option: A

NA



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