For a pipelined CPU with a single ALU, consider the following

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For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1st instruction uses the result of the j th instruction as an operand.
2. The execution of a conditional jump instruction.
3. The j th and (j + 1) st instrution require the ALU at the same time. Which of the above can cause a hazard?

1. 1 and 2
2. 2 and 3
3. 3 only
4. All

Correct Option: D

Case 1 is here of data dependency, this can’t be safe with single ALU so read after write.
Case 2 Conditional jumps are always hazardous as they create conditional dependency in pipeline.
Case 3 This is write after read problem or concurrency dependency so hazardous. All the three are hazardous. Hence (d) is correct option.