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Instruction execution in a processor is divided into 5 stages. Instruction Fetch (IF). Instruction Decode (ID). Operand Fetch (OF). Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10, and 3 nanoseconds (us) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementations of the processor are contemplated :
(i) a naive pipeline implementation (NP) with 5 stages and
(ii) an efficient pipeline (EP) where the OF stage is divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively. The speedup (correct to two decimal places) achieved by EP over NP in executing 20 independent instructions with no hazards is _______ .
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- 21
- 1.508
- 1.132
- 12.54
Correct Option: B
Given for Native pipeline, the number of stages (k) = 5.
tP1 = Max(Stage delay + buffer delay)
Buffer delay = 2nS
Stage delay = 5, 4, 20, 10, 3
So
tP1 = Max((5 + 2), (4 + 2), (20 + 2), (10 + 2), (3 + 2))
= Max (7, 6, 22, 12, 5)
Maximum value is 22.
| tP1 |
Number of instruction (n) = 20
So, execution time for native pipeline (NP).
Then,
Execution time (TNP) = (k + n – 1) tP1
= (5 + 20 – 1) 22 n sec.
TNP = 528 n sec.
Now, for efficient pipeline (TEP), the number. of stages (k = 6), n = 20, tP2 = ? tP2 = Max (Stage delay + Buffer delay)
= (12 nS + 2 nS) = 14 ns.
So, TEP = (k + n – 1) tP2
= (6 + 20 – 1) * 14 = 350 n sec.
| Speed up (S) = | = | = 1.508 | ||
| TEP | 350 |
