Consider a non-pipelined processor with a clock rate of

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Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipelined delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is _____.

1. 2.1
2. 6.2
3. 12
4. 3.2

Correct Option: D

Speed up =	Old execution time
	New execution time

=	CPI_old
	CF_old

	CPI_new
	CF_new

(where CF is clock frequency and CPI is cycles per intruction. So, CPI / CF gives time per instruction)

=	4
	2.5	= 3.2

	1
	2

Without pipelining an instruction was taking 4 cycles. After pipelining to 5 stayes we need to see the maximum clock cycle a staye can take and this will be the CPI assuning no stalls.