A CPU has a cache with block size 64 byte. The main memory has k banks, each bank being c byte wide. Consecutive cbyte chunks are mapped on consecutive banks with wraparound. All the k blanks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of parallel bank accesses depending on the amount of data obtained by accessing all the k banks is parallel. Each iteration requires decoding the bank numbers to be accessed in parallel and this takes k / 2 ns. The latency of one bank access is 80 ns. If c = 2 and k = 24, the latecy of retrieving a cache block starting at address zero from main memory is