Direction: A computer uses 46-bit virtual address, 32-bit physical address and a three-level paged page table organisation. The page table base register stores the base address of the first-level table (T₁), which occupies exactly one page. Each entry of T₁ stores the base address of a page of the second-level table (T₂). Each entry of T₂ stores the base address of a page of the third-level table (T₃). Each entry of T₃ stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.